Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. Excessive degrees of surface non-planarity will undesirably affect the quality of several semiconductor manufacturing process including, for example, photolithographic patterning processes, where the positioning the image plane of the process surface within an increasingly limited depth of focus window is required to achieve high resolution semiconductor feature patterns.
In the formation of conductive interconnections, copper is increasingly used for forming metal interconnects such as vias and trench lines since copper has low resistivity and good electromigration resistance compared to other traditional interconnect metals such as aluminum. The undesirable contribution to electrical parasitic effects by metal interconnect residual resistivity has become increasingly important as device sizes have decreased. One problem with the use of copper relates to its relatively high degree of softness making it subject to high differential material removal rates compared to adjacent dielectric insulating oxide materials during planarization processes such as chemical mechanical polishing (CMP).
CMP planarization is typically used several different times in the manufacture of a multi-layer semiconductor device. For example, CMP is used as one of the processes in preparing a layered device structure in a multi-layer device for subsequent processing. CMP is used to remove excess metal after filling anisotropically etched semiconductor features with metal to electrically interconnect the several layers and areas that make up a multi-layer semiconductor device.
CMP generally includes placing a process surface of the wafer in contact against a flat polishing surface, and moving the wafer and the polishing surface relative to one another. The polishing action is typically aided by a slurry which includes for example, small abrasive particles such as colloidal silica (SiO2) or alumina (Al2O3) that abrasively act to remove a portion of the process surface. Additionally, the slurry may include chemicals that react with the process surface to assist in removing a portion of the surface material, the slurry typically being separately introduced between the wafer surface and the polishing pad. During the polishing or planarization process, the wafer is typically pressed against a rotating polishing pad. In addition, the wafer may also rotate and oscillate back and forth over the surface of the polishing pad to improve polishing effectiveness.
There are also several different types of slurries used in the CMP process. The most common abrasives used are silica (SiO2), alumina (Al2O3), ceria (CeO2), titania (TiO2), and zirconia (ZrO2). The abrasives are typically formed using two different methods that result in fumed and colloidal abrasives. Fumed abrasives include agglomerated particles that are larger in size than the dispersed, discrete particles of colloidal abrasives. For the same solids concentration, the removal rate using a fumed abrasive is higher than that using a colloidal abrasive due to sharp edged particle features and a broader particle size distribution in fumed abrasives. For the same reasons, the defect density using a fumed abrasive also tends to be higher.
To minimize defect formation, the colloidal abrasives having a more uniform particle size distribution are preferred. However, to achieve the same material removal rate as using a fumed abrasive, the solids concentration of a colloidal slurry must be almost three times higher. The higher required solids concentration undesirably increases the cost of the slurry and leads to difficult to clean surface residues.
One particular problem with the prior art methods of CMP involve the unique problems associated with the use of low-k (low dielectric constant) materials as an inter-layer dielectric (ILD) together with copper filled features. For example, poor adhesion between the copper and the low-k material causes peeling back of the ILD layer at the copper sidewall to occur upon subjecting the polishing surface to CMP stresses. Other defects associated with CMP of copper together with low-k materials include erosion along the ILD layer/copper feature interface (feature sidewall erosion) in both relatively wide copper areas such as bonding pads and relatively long and narrow copper filled areas such as trench lines having high pattern density.
Further, the lower strength of the low-k materials has led to increased vulnerability of copper/low-k systems to CMP induced defects caused by slurries using abrasives with relatively high hardness such as fumed alumina and silica. On the other hand, slurries with colloidal particles including alumina and silica require excessively high solids content which is believed to contribute to feature sidewall erosion and difficult to clean surface residues. For example, typical slurries in the prior art have included a relatively high solids content of about 6% to about 25% by volume. The relatively high solids content tends to increase polished material residue and slurry residue accumulation within eroded or dished portions of the surface requiring extensive cleaning processes to fully remove the accumulated residues. In addition, other chemical characteristics of prior art slurries such as pH and polishing methods adapted for polishing one layer of material in a copper CMP process may not be conducive to achieving optimal surface planarity during the polishing of other material layers underlying the copper layer. As such, it has been difficult to develop CMP methods including abrasive slurries that can accomplish both requirements of an acceptable material removal rate while minimizing the introduction of defects at the semiconductor wafer surface including feature sidewall erosion.
For example, referring to FIG. 1A, a cross sectional side view of a portion of a semiconductor wafer is shown having a copper filled feature e.g., 12, for example a bonding pad or trench line, is formed in ILD layer 14A by an anisotropic etching process. The feature is typically filled with copper layer 16B by an electroplating process after forming an adhesion/barrier layer e.g., 16A, for example tantalum nitride (TaN) to line the feature opening. The feature openings are anisotropically etched into a low-k dielectric material ILD layer 14A formed of, for example, carbon or fluorine doped oxide, and one or more layers of an oxide 14B, for example having an ARC coating, for example formed of silicon oxynitride (e.g., SiON) and an optional oxide capping layer, for example SiO2, formed overlying the ILD layer 14A.
Referring to FIG. 1B, in a typical CMP process, the excess copper in copper layer 16B above the feature level is first removed followed by removal of an overlying adhesion/barrier layer 16A above the feature level. Finally an oxide CMP polishing process, using a slurry containing a polishing formulation according to the prior art is then used to remove the oxide layer 14B and buff or remove residual scratches in the ILD layer 14A. During the polishing process, feature sidewall erosion, for example as shown at 18A at the ILD layer/copper interface forms a sidewall recess with acts to trap slurry and polished material residue. In addition, peeling of the ILD layer away from the copper filled feature during CMP frequently occurs. Further, the presence of recessed areas in the copper feature surface caused by dishing or erosion during the CMP process compromises device electrical reliability.
For example referring to FIG. 1C is shown a feature profile at line A1 as obtained by a profilometer measurement of a copper filled bonding pad following a CMP process including an oxide polishing process according to the prior art. Shown on the vertical axis is relative depth in Angstroms from the wafer surface adjacent the copper bonding pad. Shown on the horizontal axis is the distance in microns along the wafer surface including the copper bonding that the profilometer is passed over (scan length). The sidewall recesses are indicated at A2 and A3 having a depth of about 1400 Angstroms.
Therefore, there is a need in the semiconductor art to develop a slurry composition and method for polishing a metal filled semiconductor feature to reduce CMP induced defects including sidewall feature erosion.
It is therefore an object of the invention to provide a slurry composition and method for polishing a metal filled semiconductor feature to reduce CMP induced defects including sidewall feature erosion while overcoming other shortcomings and deficiencies in the prior art.